November 18, 1999

Addressable field emitter array for scaling volume of chips from electron beams

In the addressable field emitter array concept, electron beams from amorphous diamond cathodes "write" circuit patterns onto a computer chip wafer. The technology could help chip makers attain the degrees of chip density that designers are approaching.

Researchers at ORNL are developing a method of packing more circuitry into a smaller space on these silicon wafers. Referred to as 100-nanometer lithography, the term reflects the feature resolution required to pack extremely tiny circuits directly onto the microchip wafers.

Immersion lithography is used to take 193-nanometer lithography and enable 22nm node features

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