Because flash-memory chips are made with silicon, their storage capacity has consistently increased, while chip size has shrunk. But, like microprocessors, flash memory will face fabrication hurdles in the next few years. Right now, the features on many flash-memory chips are about 60 nanometers wide. Some engineers estimate that today's lithography systems, used to pattern and carve out these features, will only be able to keep shrinking them until about 2009. And even then, the chips face physical limitations. Samsung's Jung says that with features smaller than 30 nanometers, electrical charges stored in a flash-memory cell will start to leak, meaning data will be lost.
So the Samsung researchers set out to find a way to use existing fabrication technology to increase flash capacity. Jung says that two elements were key: minimizing the amount of extra area used for their stacking architecture, and keeping the number of extra fabrication steps to a minimum, so as not to drive up costs.
Although Samsung didn't offer a specific timeline for its 3-D flash memory, Jung says that it could "be rapidly deployed because it can fully utilize existing 2-D planar technology. The prototype memory chip announced in San Francisco is still in its early stages and only has a capacity of 32 bits. Still, the results are encouraging. "I think it's an interesting demonstration of concept," says Subramanian. "The fact that they got it to work and they're getting very good electrical data, and the fact that the multiple layers built on top of each other work pretty nicely, is attractive."
Yet Subramanian cautions that the technology for 3-D flash still needs to prove its manufacturability. Even with Samsung's results, adding layers of silicon increases the number of steps in the process and ultimately makes the chip more expensive. "Flash memory is very driven by price, and it's a very cutthroat business," he says.
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