UPDATE: The EEtimes has more information on Intel's chip plans for more powerful and lower energy usage chips
Intel is developing "adaptive circuits" within a processor that would determine the minimum amount of performance required for a task. "We have a brain in the chip," Bryan Casper, principal engineer for Intel's Circuit Research Lab in Hillsboro, said. All power associated with a task is turned down to a "just-enough" level.
A prototype of the technology was demonstrated in a PCI Express card with a chip that consumed one-tenth the power of a card with today's chip technology, or 2.7 milliwatts versus 20 to 30 milliwatts. Reducing power consumption is critical, given that using today's technology to power a PCI Express card with a bandwidth of a terabit per second would require 100 watts of energy, Casper said.
Researchers showed a prototype of a Wi-Fi card with firmware that automatically turned off the power when the card was not in use. The technology also knew when to power up to receive or transmit data packets. Such cards use from 50% to 70% less power than standard wireless cards, researchers said.
Harrison demonstrated a pager-size device that could be hooked on a belt, and sense whether the wearer was bicycling, running, standing, using a Stairmaster exercise machine, or walking. In the demo, the device's choice was displayed on a screen in the form of percentages, since power walking, for example, could be considered half walking and half running. The idea behind the research is to make computing as unobtrusive as possible in everyday life.
Intel is working on Larrabee which will likely start out having 3 teraflops of performance and will compete with the general purpose GPUs like Nvidia Tesla.
Package size: 49.5mm x 49.5mm
Intel will try to get it out in 2008
Intel will continue to release more cores on its best chips
Compilers from Intel and Microsoft and others are being adapted to the high number of core and lots of threads world
Some of the existing computational chemistry applications are well suited to massively parallel hardware. Others like ACES II will be ported to the new systems. Nanoengineer-1 and others systems will get a lot faster.
Solid state flash memory has been improving at a faster than Moore's law rate
Enterprise solid state flash drives have higher capacities and faster data connections. Availability of solid state drives at wikipedia
Simple tech has 256 GB drives now for $10,000 while the 512GB version will follow in Q3 2007 for $15,000.
Basic sub $1000 SSD flash drives as of 2007 are delivering about 5000 to 10,000 IO per second (IOPS compared to 500 for faster hard drive arrays. More expensive systems can provide 100,000 IOPS or more.
An article addresses the limited write cycle issue of flash drives as a non-issue now
If Dwave quantum computers pan out, then there will 1000 qubits by the end of 2008 It will 2009, before the Dwave system is adapted or molecular simulation and probably 4000 qubits.
A projection of what this might mean for computational chemistry.
so by the end of 2007, $60,000 for 12 teraflops, $10,000 for a nice 8-core workstation, $15,000 for 512 GB of enterprise solid state flash drive. 100 times faster how much you would buy in early 2007.
By the end of 2008, $60,000 double precision and 36 teraflops, $10,000 for nice 32 core system, $20,000 for 2 Terabytes of enterprise solid state flash drive. 300 times faster than what could be bought in early 2007.
by the end of 2009, $60,000 for 100 Teraflops, $10,000 for nice 80 core system, $20,000 for 4 Terabytes of enterprise solid state flash, 4000 qubit quantum computing molecular simulator. 900+ times faster than what could be bought in early 2007.